Jichuan Chang

I'm a Research Scientist at Google currently working on computer systems and architecture. My research focuses on designing efficient systems for large-scale data processing and warehouse computing environments. I previously did research at HP Labs and the University of Wisconsin-Madison working with Guri Sohi and other collaborators. My work spans several key areas including memory systems, cache architectures, and data center design. I've made contributions to cooperative caching for chip multiprocessors, memory disaggregation in blade servers, and profiling/acceleration techniques for hyperscale data processing. Recently, I've been exploring ways to optimize system architectures for emerging workloads in warehouse-scale computers, with a focus on improving performance, energy efficiency, and total cost of ownership.
Throughout my career, I've aimed to take a holistic approach to system design - considering not just performance but also power, cost, reliability and environmental impact. My research often involves building real systems and prototypes to validate new architectural ideas. I collaborate extensively across industry and academia to tackle important challenges in large-scale computing infrastructure.

Publications

Profiling Hyperscale Big Data Processing

Abraham Gonzalez, Aasheesh Kolli, S. Khan, Sihang Liu, Vidushi Dadu, S. Karandikar, Jichuan Chang, K. Asanović, Parthasarathy Ranganathan

International Symposium on Computer Architecture 2023

ABS PDF

Software-Defined Far Memory in Warehouse-Scale Computers

Andres Lagar-Cavilla, Junwhan Ahn, Suleiman Souhlal, Neha Agarwal, Radoslaw Burny, S. Butt, Jichuan Chang, Ashwin Chaugule, Nan Deng, Junaid Shahid, Greg Thelen, Kamil Adam Yurtsever, Yu Zhao, Parthasarathy Ranganathan

International Conference on Architectural Support for Programming Languages and Operating Systems 2019

ABS PDF

Learning Memory Access Patterns

Milad Hashemi, Kevin Swersky, Jamie A. Smith, Grant Ayers, Heiner Litz, Jichuan Chang, Christos Kozyrakis, Parthasarathy Ranganathan

International Conference on Machine Learning 2018

ABS PDF

Buri

Jishen Zhao, Sheng Li, Jichuan Chang, John L. Byrne, Laura L. Ramirez, Kevin T. Lim, Yuan Xie, P. Faraboschi

ACM Transactions on Architecture and Code Optimization (TACO) 2015

ABS PDF

Near-Data Processing: Insights from a MICRO-46 Workshop

R. Balasubramonian, Jichuan Chang, Troy Manning, J. Moreno, R. Murphy, R. Nair, S. Swanson

IEEE Micro 2014

Jichuan Chang

Publications

Profiling Hyperscale Big Data Processing

Software-Defined Far Memory in Warehouse-Scale Computers

Learning Memory Access Patterns

Buri

Near-Data Processing: Insights from a MICRO-46 Workshop

Author retrospective for cooperative cache partitioning for chip multiprocessors

Practical nonvolatile multilevel-cell phase change memory

Hardware acceleration for similarity measurement in natural language processing

Efficient virtual memory for big memory servers

Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management

BOOM: Enabling mobile memory based low-power server DIMMs

Workload diversity and dynamics in big data analytics: implications to system designers

Accès à une mémoire

A limits study of benefits from nanostore-based future data-centric system architectures

Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism

Totally green: evaluating and designing servers for lifecycle environmental impact

System-level implications of disaggregated memory

System-level integrated server architectures for scale-out datacenters

Power-efficient networking for balanced system designs: early experiences with PCIe

FREE-p: Protecting non-volatile memory against both hard and soft errors

Green server design: beyond operational energy to sustainability

Saving the World, One Server at a Time, Together

Disaggregated memory for expansion and sharing in blade servers

Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments

Cooperative cache partitioning for chip multiprocessors

Cooperative Caching for Chip Multiprocessors

Speculative Incoherent Cache Protocols

Coherence decoupling: making use of incoherence

Software component composition based on ADL and Middleware

PicoServer Revisited: On the Profitability of Eliminating Intermediate Cache Levels

(Re)Designing Data-Centric Data Centers

Disaggregated Memory Benefits for Server Consolidation

Is Storage Hierarchy Dead? Co-located Compute-Storage NVRAM-based Architectures for Data-Centric Workloads

LIFECYCLE-BASED DATA CENTER DESIGN

Data dwarfs: Motivating a coverage set for future large data center workloads

SERVER DESIGNS FOR WAREHOUSE

Server Designs for Warehouse-Computing Environments

Partitioning a memory pool among plural computing nodes

Cooperative cache partitioning for chip multiprocessors

Speculative incoherent cache protocols

Dynamic Architecture-Based Monitoring

Investigating the Consensus Problem in HLA Bridge

Using Gauges for Architecture-Based Monitoring and Adaptation

Composing Software Components at Architectural Level

JBCDL: An Object-Oriented Component Description Language

More on Conjunctive Selection Condition and Branch Prediction CS 764 Class Project-Fall 2002

Point de contrôle local utilisant une cellule multi-niveau